A DRAM consists of an arrangement of individual memory cells. Each memory cell comprises a capacitor capable of holding a charge and a field effect transistor, hereinafter referred to as an access transistor, for accessing the capacitor charge. The charge is referred to as a data bit and can be either a high voltage or a low voltage. Therefore, the memory has two states; often thought of as the true logic state and the complementary logic state. An arrangement of memory cells is called an array. There are two options available in a DRAM memory: a bit of data may be stored in a specific cell in the write mode, or a bit of data may be retrieved from a specific cell in the read mode. The data is transmitted on signal lines, also called digit lines, to and from the Input/Output lines, hereinafter known as I/O lines, through field effect transistors used as switching devices and called decode transistors. For each bit of data stored, its true logic state is available at the I/O lines and its complementary logic state is available at lines designated I/O*. For purposes of this discussion, I/O and I/O* lines are often referred to as just I/O lines. Therefore, each cell has two digit lines, referred to as digit line pairs.
In order to read from or write to a cell, the particular cell in question must be selected, also called addressed. Typically, the cells are arranged in the array in a configuration of intersecting rows and columns. In order to select a cell an active output from the row decoder selects a wordline appropriate to the given address. The active wordline then turns on the cell's access transistor. Next the column decoder activates and selects the desired digit line pair. For a write operation the active column decoder output activates the decode transistors to pass the data to be written from the I/O lines to the digit line pair. The data is then coupled through the access transistor to the memory cells which then store the data.
FIG. 1 represents a video display. The video display displays data stored in a memory device. The memory device is typically referred to as a video random access memory (VRAM) device. One example of a video display is a color or monochrome monitor for a personal computer. The data must be pumped to the video display by the VRAM. Each location on the video display is called a pixel.
The VRAM typically contains a DRAM memory in which pixel data is stored and a serial access memory (SAM) port. The data is usually loaded into the VRAM through a DRAM port. The pixel data is typically stored in the DRAM and supplied to the video display through a SAM port.
FIG. 1 is a simplified representation of a video display having 64 pixels. There are different methods employed to get pixel data into the DRAM memory. One method comprises computing a value representing the color of the data and computing an address for each pixel representing the data. The DRAM cycles once for each pixel. For example if the data is represented by the five pixels 1, the DRAM goes through five cycles in order to store the pixel data into the DRAM memory.
A second method can increase the speed of inputing the data into the DRAM. This method is called a block write. The block write method computes a value and an address for four pixels simultaneously. The four pixels comprise the block. The DRAM cycles once for each block of four pixels stored in the DRAM. In this method four pixels are typically accessed in each cycle. It would therefore require two cycles to implement the previous example wherein the data is defined by five pixels.
A third method of loading the data into the DRAM can increase the speed over the block write. This method is called a flash write. In a flash write all of the column addresses for a given row are loaded in one cycle. The disadvantage of the flash write is the inability to load only a portion of the column addresses for a given row.
Since a specific address is used to identify each pixel there must be a method for decoding that address. A column decoder is typically used to decode the address. A tree type column decoder is typically used as the column decoder. The tree column decoder is implemented in a NOR configuration such that when the proper inputs are low the desired column decoder output goes high.
Micron Semiconductor, Inc. distributes a "1992 DRAM Data Book," of which sections 3 and 1 are hereby incorporated by reference, containing detailed descriptions of Micron's VRAM devices. An article published in Electronic Design Nov. 23, 1989, entitled "Speed Memory, Ease Timing Requirements With VRAM Functions," by Mailloux, et al., describes many of the features used to speed data transfer to and from an associated graphics processor or microprocessor and is also incorporated by reference.